1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for processing a semiconductor substrate.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabrication of an integrated circuit involves numerous processing steps. To form a metal-oxide-semiconductor (MOS) integrated circuit, for example, a gate dielectric, typically formed from silicon dioxide (xe2x80x9coxidexe2x80x9d), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form source and drain regions. Such transistors may be connected to each other and to terminals of the completed integrated circuit using conductive interconnect lines. In addition, the fabrication of MOS transistors typically includes the formation of isolation structures between the active areas of the substrate. In general, the isolation structures may define the field regions of the semiconductor substrate, while the area including transistors may define the active areas of the substrate.
A technique known as xe2x80x9cphotolithographyxe2x80x9d is generally used to pattern various structures of an integrated circuit during its fabrication process. In general, photolithography entails transferring an optical image to a photosensitive film from a patterned mask plate (i.e., reticle) placed between the light source and the film. Such a process may include coating the photosensitive film, i.e., xe2x80x9cphotoresistxe2x80x9d upon a semiconductor topography to be patterned. A mask plate having both opaque and transparent regions may be placed above the photoresist and radiation may be transmitted through the transparent regions of the mask plate to the photoresist. The solubility of resist exposed to the radiation is altered by a photochemical reaction. Subsequently, a solvent may be used to remove the resist areas of higher solubility. The resulting patterned resist film may serve to protect underlying conductive or dielectric material from etching processes or ion implantation. Consequently, structures of an integrated circuit may be formed having a similar lateral layout to the pattern of the overlying photoresist. In some embodiments, an anti-reflective layer may be interposed between the photoresist and the semiconductor topography in order to prevent the reflection of energy rays. Such a reflection of rays may undesirably alter the pattern of the photoresist by exposing additional portions of the photoresist. In addition or alternatively, the reflected energy rays may produce standing waves within the photoresist during exposure and result in an undesirably ragged post-develop photoresist profile.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Smaller feature sizes may allow more transistors to be placed on a single substrate. In addition, transistors with smaller feature sizes may function faster and at a lower threshold voltage than transistors having larger feature sizes. The feature sizes of a transistor, however, may be limited by the image resolution of the photolithographic equipment used to form the transistor. Such image resolution is typically dependent on the wavelength of the photolithographic tool. For example, the minimum resolvable feature size of a 248 nm photolithographic tool may be approximately 0.14 microns. As such, in order to obtain a structure with a feature size with a dimension smaller then approximately 0.14 microns, a smaller wavelength photolithographic tool may need to be used.
However, there are disadvantages with using smaller wavelength photolithographic tools. For example, photolithographic tools are typically expensive and therefore, purchasing new photolithographic tools for each new development of transistors with reduced feature sizes may be cost prohibitive. Furthermore, smaller wavelength photolithographic tools used to produce such transistors may require substantial process development to produce such small feature sizes. In addition, the materials used for photoresist films and underlying anti-reflective layers may be dependent on the wavelength used with the photolithographic tool and therefore, may need to be revised for consistency with the new photolithographic tools. In some cases, problems, such as poor image resolution, poor etch selectivity, or patterning clarity such as line edge roughness, may arise with such immature technologies and chemistries. As a result, the installation of new photolithographic equipment and its associated chemistry may delay the development of transistors of reduced feature sizes.
One method of producing transistor structures with dimensions smaller than the dimensions obtainable by a photolithographic tool used to pattern the structure is sometimes referred to as xe2x80x9ctrimming.xe2x80x9d xe2x80x9cTrimmingxe2x80x9d typically includes etching the periphery of a patterned structure underlying a photoresist layer such that dimensions of the structure are reduced. Such a technique typically reduces the length and width of the patterned structure. However, a reduction in both the length and the width may be undesirable in some cases. For example, during the fabrication of gate structures, it may be desirable to reduce the width of a gate structure in order to decrease the channel length of the subsequently formed transistor. However, each end of the gate structure typically needs to extend partially over an isolation region in order to prevent a short from occurring between the gate""s source and drain regions. Unfortunately, xe2x80x9ctrimmingxe2x80x9d may undesirably shorten the length of the gate structure such that one or more of its ends no longer extends over an isolation region. As a result, the subsequently formed transistor may have decreased performance or in some cases may fail to function. In some cases, the transistor fabrication process may require forming larger isolation regions to separate active areas of the transistor in order to insure that the ends of the subsequently trimmed gate structure extend over isolation regions. Such an embodiment may undesirably reduce the active area of the wafer. Consequently, fewer transistors may be fabricated on a single wafer, thereby reducing the advantage of reducing the feature size of the transistor.
It would, therefore, be advantageous to develop a method for forming a semiconductor structure with a dimension smaller than what is obtainable by the photolithographic equipment used to fabricate the structure. In particular, it would be advantageous to develop such a method that does not undesirably reduce one or more other dimensions of the structure.
The problems outlined above may be in large part addressed by a method for processing a semiconductor topography. In particular, a method is provided for forming device components laterally spaced within a semiconductor topography. More specifically, a method is provided for fabricating a device, which includes device components and one or more spacings there between that may each have a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components. In particular, the method may be used to form a spacing that has a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components arranged adjacent to the spacing. In some embodiments, the method may be used to form device components and spacings there between that are arranged along a first dimension parallel to an underlying substrate of the semiconductor topography.
The method may include, for example, patterning an upper layer of the semiconductor topography using a photolithography process to form a first feature having dimensions substantially equal to or greater than the minimum dimension obtainable by the photolithography process. In some cases, the first feature may be a device mask. In such an embodiment, the method may include trimming the device mask and forming a semiconductor structure within underlying layers of the semiconductor topography in alignment with the trimmed device mask. In addition, the method may include patterning the formed semiconductor structure to form device components and spacings therebetween. In another embodiment, the first feature may include an opening. In such a case, the method may include forming a trench within underlying layers of the semiconductor topography in alignment with the opening and subsequently forming one or more device components adjacent thereto.
In general, forming the trench and/or patterning the semiconductor structure may include tapering the first layer of the underlying layers to expose a portion of a second layer of the underlying layers and removing the exposed portion of the second layer. In a preferred embodiment, tapering the first layer of the underlying layers may include exposing the semiconductor topography to an etch chemistry comprising CH3F/O2, wherein the ratio of CH3F to O2 is between approximately 5:1 and approximately 10:1. In addition or alternatively, the tapering process may include setting a temperature of a chuck on which the semiconductor topography is positioned. Such a temperature setting may be between approximately 0xc2x0 C. and approximately 10xc2x0 C. In either or both cases, tapering the first layer of the underlying layers may include tapering the first layer to an angle between approximately 60 degrees and approximately 90 degrees relative to the upper surface of the second layer. In addition, removing the exposed portion of the second layer may include etching the second layer. In some cases, removing the exposed portion of the second layer may include tapering at least an upper portion of the exposed portion of the second layer. In such an embodiment, tapering a portion of the second layer may include exposing the semiconductor topography to an etch chemistry comprising Cl2/HBr, wherein the ratio of HBr to Cl2 is between approximately 5:1 and approximately 10:1.
As stated above, the method may include patterning an upper layer of a semiconductor topography using a photolithography process to form a device mask having dimensions substantially equal to or greater than the minimum dimension obtainable by the photolithography process. Such a method may further include trimming the device mask. In some cases, the trimming process may include etching an intermediate layer arranged beneath the upper layer. Such an intermediate layer may be an antireflective layer, for example. The method may proceed by forming a semiconductor structure within underlying layers of the semiconductor topography in alignment with the trimmed device mask. In a preferred embodiment, the semiconductor structure may be patterned to form one or more device components. In this manner, the semiconductor structure may be a transitional structure. In some cases, the method may include removing remaining portions of the upper layer and intermediate layer prior to patterning the transitional structure. The removal of the remaining portions of the intermediate layer may be particularly advantageous when the intermediate layer includes organic material. In other embodiments, the method may include removing only remaining portions of the upper layer prior to patterning the transitional structure. In such an embodiment, the intermediate layer may include inorganic material.
In some cases, the method may further include depositing one or more additional layers upon the semiconductor topography subsequent to patterning the upper layer. More specifically, the method may include depositing one or more additional layers upon the semiconductor topography subsequent to forming the first feature. For example, the method may include depositing one or more additional layers upon the semiconductor topography subsequent to forming a trench. In another embodiment, the method may include depositing one or more additional layers upon the semiconductor topography subsequent to forming a semiconductor structure. In particular, the method may include depositing one or more layers upon the semiconductor topography prior to patterning the semiconductor structure. More specifically, the method may include depositing one or more layers upon the semiconductor topography prior to tapering the first layer of the underlying layers for patterning the semiconductor structures.
In some embodiments, depositing the one or more layers may include depositing an anti-reflective layer and a photoresist layer. In such an embodiment, tapering the first layer of the underlying layers to form a trench may include removing portions of the antireflective layer. In addition or alternatively, removing the exposed portion of the second layer of the underlying layers to form the trench may include removing portions of the antireflective layer. In some embodiments, the method may further include etching remaining portions of the anti-reflective layer subsequent to removing the exposed portion of the second layer. Such an etch process may preferably include an etch chemistry which is selective to the anti-reflective layer as compared to the materials of the remaining portions of the first and second layers. In other words, the etch chemistry used to remove remaining portions of the antireflective layer may be substantially absent of substances which may actively etch the materials of the first and second layers. For example, the etch chemistry used during such an etching process may be substantially absent of hydrofluoric acid.
In either embodiment, the one or more additional layers may be patterned using a photolithography process to form a second feature having a dimension substantially equal to or greater than the minimum dimension obtainable by the photolithography process used to form the second feature. In some embodiments, the photolithography process used to form the second feature may be similar to the photolithography process used to form the first feature. Alternatively, the photolithography process used to form the second feature may be different from the photolithography process used to form the first feature. In some cases, the second feature may include an opening arranged above a semiconductor structure or a transitional structure. In such an embodiment, the method may include forming a trench within the semiconductor structure and in alignment with the opening. In this manner, the method may include patterning the one or more additional layers to expose the first layer of the semiconductor structure or transitional structure. In an alternative embodiment, the second feature may include a device mask arranged adjacent to a trench filled with the one or more additional layers. In such a case, the method may include forming device components within underlying layers of the semiconductor topography in alignment with the device mask and adjacent to the trench.
A device is provided herein which includes one or more components having a dimension smaller than a minimum dimension obtainable by photolithographic equipment used to fabricate the device. For example, in an embodiment in which a 248 nm lithographic tool is used to fabricate the device, the minimum dimension obtainable by the tool may be approximately 0.14 microns. Consequently, the device may include components having a dimension smaller than approximately 0.14 microns. In some embodiments, the device may be an integrated circuit. In another embodiment, the device may include a micromechanical device. In either embodiment, the device components may include, for example, processing structures such as gate electrodes or interconnect lines. In one embodiment, the device components may include conductive ribbons used in grating light valve (GLV) micromechanical devices. In a preferred embodiment, the device components may be arranged such that a width of a spacing between two adjacent components is smaller than the minimum dimension obtainable by the photolithographic equipment. In some embodiments, the width of the spacing may be between approximately 30% and approximately 100% of the minimum dimension. More specifically, the width of the spacing may be between approximately 50% and approximately 80% of the minimum dimension. In some embodiments, the device may further include an isolation region arranged beneath the spacing. In some cases, an end of at least one of the components may be arranged over such an isolation region.
The method described herein may offer several benefits. In particular, the method may be used to fabricate a device that has smaller feature sizes than are obtainable by the photolithographic equipment used to pattern the features. Devices with smaller feature sizes may operate at faster speeds and lower voltages. As such, the method may be used to fabricate devices, such as integrated circuits and micromechanical devices, with greater functional characteristics than devices having dimensions equal to or larger than the minimum obtainable dimension of the photolithographic equipment used to pattern the components of the devices. In addition, the method may be used to fabricate a device with smaller dimensions than are obtainable by the photolithographic equipment used to pattern the features of the device without sacrificing other dimensions of the device. For example, the method may allow a gate electrode to have a width smaller than is obtainable by a photolithographic process. However, such a method may not reduce the length of the gate electrode. In this manner, the ends of the gate electrode may extend over isolation regions as required by the design of the device. Moreover, such a method may advantageously allow additional photolithographic equipment purchases to be avoided. Consequently, such a method may drastically reduce fabrication costs.